In complex semiconductor circuits such as DRAMs (dynamic random access memories), the test costs are a significant part, currently approximately 15% to 20%, of the total production costs. Semiconductor circuits are normally tested on programmable test apparatuses (e.g., component testers). To increase the throughput of semiconductor circuits to be tested on the cost-intensive test apparatuses, short test times and a high level of test parallelism are the aim. The test time is prescribed by the functionality of the semiconductor circuit. The number of semiconductor circuits which can be tested simultaneously on a test apparatus is limited by the number of test channels in the test apparatus.
To increase the throughput on the test apparatuses, “reduced-I/O” test methods are therefore customary, requiring contact to be made only with some of the signal connections on the semiconductor circuit to be tested. In a reduced-I/O test method with a self-test unit inside the component, the functionality of internal circuits in the semiconductor circuit is tested by an internal self-test. The signal connections coupled to the test apparatus are used merely to initiate the internal self-test and to transmit a test result for the self-test to the test apparatus. The number of test channels required per semiconductor circuit is significantly reduced.
Further reduced-I/O test methods are scanpath and boundary scan test methods, whose performance requires contact to be made with a subset of the signal connections on the semiconductor circuit to be tested.
Disadvantageously, conventional reduced-I/O test methods do not test the signal connections which are unused during the test and are not coupled to the test apparatus, or the input or output switching arrangements (I/O pads, pad circuits) associated with the unused signal connections. Besides the signal connection, an I/O pad comprises an output driver, which is able to drive an output signal generated by internal circuits in the semiconductor circuit on a signal line coupled to the signal connection, and/or an input driver, which conditions an input signal applied to a signal connection in a manner which is suitable for the internal circuits, and also a connecting line between the signal connection and the input or output driver.
In the simplest case, the I/O pads which are not tested in the course of a reduced-I/O test method are tested by a further pass on the same or on another test apparatus, in which case, with an appropriately low level of test parallelism, all signal connections on the semiconductor circuit to be tested are coupled to a respective test channel in the test apparatus.
Japanese patent number JP-09-257884 A describes a test method for unidirectional input drivers in a semiconductor circuit, in which the input drivers are connected, in a test mode, to a ring oscillator via controllable selector circuits in order to test the basic functionality of the input drivers by evaluating the oscillation by the ring oscillator. In this context, the selector circuits are respectively connected between the input of the input driver and the respective associated signal connection.
German patent number DE 101 38 556 C1 (Oberle, Sattler) describes one option for testing bidirectional I/O pads with which there is no contact within the context of a reduced-I/O test method, which option involves the bidirectional I/O pads being tested by returning a test signal via the output driver for the I/O pad to the input of the input driver for the same I/O pad, and from there to an evaluation logic unit inside the component. To test unidirectional I/O pads, the German patent proposes that a respective unidirectional I/O pad with an input driver and a unidirectional I/O pad with an output driver be coupled to one another outside of the semiconductor circuit.